Bringing test to design: Testing in the designer's event based environmentRAJSUMAN, Rochit.IEEE/CPMT International Electronics Manufacturing Technology Symposium. 2002, pp 372-375, issn 1089-8190, isbn 0-7803-7301-4, 4 p.Conference Paper

An optimal PCM Codec Soft IP Generator and its applicationWU, Gwo-Yang; CHEN, Liang-Bi; JEANG, Yuan-Long et al.IEEE international conference on field-programmable technology. 2002, pp 315-317, isbn 0-7803-7574-2, 3 p.Conference Paper

Efficient post-layout power-delay curve generationVUJKOVIC, Miodrag; WADKINS, David; SECHEN, Carl et al.Lecture notes in computer science. 2005, pp 393-403, issn 0302-9743, isbn 3-540-29013-3, 11 p.Conference Paper

A VHDL-AMS package for micro-systems polychromatic optical modelingQUIQUEREZ, Laurent; OUAAZIZ, Siomar; PITTET, Patrick et al.SPIE proceedings series. 2004, pp 364-374, isbn 0-8194-5378-1, 11 p.Conference Paper

Two approaches for developing generic components in VHDLSTUIKYS, V; ZIBERKAS, G; DAMASEVICIUS, R et al.Microelectronics journal. 2002, Vol 33, Num 3, pp 271-277, issn 0959-8324Article

Divgen : a divider unit generatorMICHARD, Romain; TISSERAND, Arnaud; VEYRAT-CHARVILLON, Nicolas et al.Proceedings of SPIE, the International Society for Optical Engineering. 2005, pp 59100M.1-59100M.12, issn 0277-786X, isbn 0-8194-5915-1, 1VolConference Paper

High-speed hardware implementations of the kasumi block cipherKITSOS, P; GALANIS, M. D; KOUFOPAVLOU, O et al.IEEE International Symposium on Circuits and Systems. 2004, pp 549-552, isbn 0-7803-8251-X, 4 p.Conference Paper

FPGA based accelerator for functional simulationWAGEEH, Mohamed N; WAHBA, Ayman M; SALEM, Ashraf M et al.IEEE International Symposium on Circuits and Systems. 2004, pp 317-320, isbn 0-7803-8251-X, 4 p.Conference Paper

Capacitive RF MEMS analytical predictive reliability and lifetime characterizationMATMAT, Mohamed; COCCETTI, Fabio; MARTY, Antoine et al.Microelectronics and reliability. 2009, Vol 49, Num 9-11, pp 1304-1308, issn 0026-2714, 5 p.Conference Paper

An efficient memory allocation algorithm and hardware design with VHDL synthesisKARABIBER, F; SERTBAS, A; OZDEMIR, S et al.International journal of electronics. 2008, Vol 95, Num 1-2, pp 125-138, issn 0020-7217, 14 p.Article

Automatic logic synthesis for parallel alternating latches clocking schemesGUERRERO, D; BELLIDO, M; JUAN, J et al.Proceedings of SPIE, the International Society for Optical Engineering. 2007, pp 659006.1-659006.9, issn 0277-786X, isbn 978-0-8194-6718-8, 1VolConference Paper

A multi-level validation methodology for wireless network applicationsDROSOS, C; BISDOUNIS, L; METAFAS, D et al.Lecture notes in computer science. 2004, pp 332-341, issn 0302-9743, isbn 3-540-23095-5, 10 p.Conference Paper

A tool for the integration of new VHDL-AMS models in spiceZORZI, M; FRANZE, F; SPECIALE, N et al.IEEE International Symposium on Circuits and Systems. 2004, pp 637-640, isbn 0-7803-8251-X, 4 p.Conference Paper

Library of Digital Circuit Development For Digital System IntegrationPUNUGOTI, Pavani; WUNNAVA, Subbarao V.IEEE Southeastcon. 2004, pp 405-409, isbn 0-7803-8367-2, 1Vol, 5 p.Conference Paper

Quantum circuit's reliability assessment with VHDL-based simulated fault injectionBONCALO, Oana; AMARICAI, Alexandru; UDRESCU, Mihai et al.Microelectronics and reliability. 2010, Vol 50, Num 2, pp 304-311, issn 0026-2714, 8 p.Article

Assertion based verification using HDVLDATTA, Kausik; DAS, P. P.International Conference on Embedded Systems DesignInternational Conference on VLSI Design. 2004, pp 319-325, isbn 0-7695-2072-3, 1Vol, 7 p.Conference Paper

Incorporating signature-monitoring technique in VLIW processorsCHEN, Yung-Yuan; CHEN, Kun-Feng.IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. 2004, pp 395-402, isbn 0-7695-2241-6, 1Vol, 8 p.Conference Paper

Compiling run-time parametrisable designsDERBYSHIRE, Arran; LUK, Wayne.IEEE international conference on field-programmable technology. 2002, pp 44-51, isbn 0-7803-7574-2, 8 p.Conference Paper

Speedup analysis in simulation-emulation co-operationSEYED GHASSEM MIREMADI; SIAVASH BAYAT SARMADI; ASADI, Ghazanfar et al.IEEE international conference on field-programmable technology. 2002, pp 394-398, isbn 0-7803-7574-2, 5 p.Conference Paper

Mixed-signal simulation and test generationDUFILS, M; CARBONERO, J. L; PLANELLE, P et al.International journal of electronics. 2008, Vol 95, Num 3, pp 239-248, issn 0020-7217, 10 p.Conference Paper

Compilation reuse and hybrid compilation : An experimentRAO LOKA, Raghavendra.ACM SIGPLAN notices. 2006, Vol 41, Num 4, pp 42-49, issn 1523-2867, 8 p.Article

VHDL-based design of FSM with concurrent error detection capabilitySTOJCEV, M. K; DJORDJEVIC, G. Lj; STANKOVIC, T. R et al.International conference on microelectronics. 2004, isbn 0-7803-8166-1, 2Vol, vol 2, 759-762Conference Paper

Functional design using behavioural and structural componentsSHARP, Richard.Lecture notes in computer science. 2002, pp 324-341, issn 0302-9743, isbn 3-540-00116-6, 18 p.Conference Paper

Proposal of synthesisable analogue-to-digital converters from VHDL-AMSDOMENECH-ASENSI, G; GARRIGOS-GUERRERO, J.International journal of electronics. 2008, Vol 95, Num 8-10, pp 891-902, issn 0020-7217, 12 p.Article

Hierarchical Modeling of a Fractional Phase Locked LoopNICOLLE, Benjamin; TATINIAN, William; OUDINOT, Jean et al.Lecture notes in computer science. 2006, pp 450-457, issn 0302-9743, isbn 3-540-39094-4, 1Vol, 8 p.Conference Paper